Semiconductor wafers find wide-ranging use in electronic devices, such as microprocessors, microcontrollers, and application-specific integrated circuits, as substrates for metal oxide semiconductor (MOS) transistors. MOS transistors generally include a gate electrode formed above the semiconductor wafer, with the gate electrode being insulated from the semiconductor wafer by a thin layer of gate insulator material. A source and a drain are spaced apart regions of either N-type or P-type semiconductor material and are generally embedded within the semiconductor wafer adjacent to the gate electrode on either side thereof. A region in the semiconductor wafer between the source and the drain, and beneath the gate electrode, forms a channel of the MOS transistor.
It is known that the mobility of charge carriers, i.e., electrons and holes, in the channel can be increased when the semiconductor wafer is stressed in the channel. Depending upon the type of transistor, different types of stress have different effects on carrier mobility. For example, the mobility of electrons in the channel of an NMOS transistor can be increased by applying a tensile stress to the channel in the semiconductor wafer, whereas the mobility of holes in the channel of a PMOS transistor can be increased by applying compressive stress to the channel in the semiconductor wafer.
Stress can be introduced into semiconductor wafers using a global approach, in which biaxial stress is introduced across a surface of the semiconductor wafer along two axes, or a local approach, in which uniaxial stress is introduced into the semiconductor wafer at discreet locations in the semiconductor wafer along a single axis. To introduce stress into semiconductor wafers using the global approach, exemplary structures including silicon germanium (SiGe) stress-relaxed buffer layers or silicon carbide (SiC) stress-relaxed buffer layers can be formed on the surface of the semiconductor wafer. To introduce stress into semiconductor wafers using the local approach, stress is introduced only to local areas adjacent to the channel of the transistor from a local structure such as, for example, a stress liner, embedded silicon SiGe source/drain structures, embedded SiC source/drain structures, and stress-generating shallow trench isolation structures. Due to easier integration within device formation processes, local approaches to introduction of stress into semiconductor wafers have generally been favored, although global approaches to introduction of stress generally enable stronger and more uniform stress to be introduced than local approaches.
In view of the foregoing, there is an opportunity to provide novel processes for preparing semiconductor wafers by which biaxial stress can be introduced into the semiconductor wafers. There is also an opportunity to provide processes for preparing devices including a stressed semiconductor wafer in which biaxial stress is introduced therein through the novel process. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.